A ceramic quad package and a ceramic flat package, hereinafter referred to as a cerquad and cerflat, respectively, typically have a ceramic base, a leadframe attached to the ceramic base with a glass, a semiconductor die mounted on the ceramic base and wire bonded to leads of the leadframe, and a ceramic cap that is glass sealed to the base to form a hermetic semiconductor device. The leadframe is produced either by an etching process or a stamping process. The lead tips of a cerquad leadframe extend on all four sides toward a central die receiving area, typically a cavity in the ceramic base, while the lead tips of a cerflat leadframe only extend on two sides. Due to the limitations of etching technology, the lead tips cannot be extend indefinitely toward the center because the tip to tip lead pitch that can be achieved is currently limited. The minimum inner lead pitch of a cerquad leadframe is approximately 0.26 millimeter (10 mils) with a lead width of 0.13 millimeter (5 mils) and a spacing of 0.13 millimeter (5 mils). The leads cannot be manufactured any closer than what is currently achievable. Stamping technology cannot produce as fine pitch of a leadframe as etching technology. Hence, leadframe etching limitations dictates a minimum leadframe cavity size in a cerquad, which translates into an effective mininum die cavity size.
Developments in semiconductor technology are causing some problems in the packaging of semiconductor dice in cerquads. Many semiconductor dice have a high number of inputs/outputs (I/Os) while the overall size of the dice is shrinking. This development leads to a high pin count, fine-pitch cerquad device. As mentioned above, the minimum inner lead pitch of a cerquad leadframe is limited. Therefore, if a semiconductor die is much smaller in size than the minimum achievable die cavity in a cerquad, problems arise. The lengths of the wire bonds become prohibitively long which can lead to a shorting problem in the device. Wire bond lengths in a single-tier package, which are longer than approximately 100 times the diameter of the wire, can sag, sweep, and deform, all of which can lead to potential shorts. Increasing the semiconductor die size will decrease the wire bond lengths but is a costly solution because less dice can be placed on a single semiconductor wafer. Moreover, to unnecessarily increase die size is contrary to the direction in the semiconductor technology toward die size reduction.
One alternative to the fine-pitch problem of a cerquad leadframe is to use brazing technology, wherein the leads are brazed onto the base. The base would be metallized to maintain electrical continuity with the brazed leads. However, this is very costly technology as compared to the glass embed leadframe approach used in a cerquad, because brazed packages are normally gold plated internally as well as externally, while cerquad packages do not require external gold plating of the leads.
There is an additional push in the electronics industry toward increasing the density of devices on a board. Multiple chip modules are becoming more widely used. Because board space is limited, one way of increasing chip density on a board is to stack devices in the Z-direction. It would be desirable to be able to stack devices to form a module, such as a memory module, and still retain hermeticity for the devices.
A need exists for a cerquad that can house a small semiconductor die having a large number of I/Os without having prohibitively long wire lengths. A need also exists for a high density yet hermetic packaging method for high reliability applications.